1. Field of the Invention
The present invention relates to a fabrication method and a structure of a through silicon via.
2. Description of the Prior Art
In the field of semiconductor technology, the response speed of IC circuits is related to the linking distance between devices disposed on a chip. For signal to be transmitted, the shorter the linking distance is, the faster the operational speed of a circuit device can be. Since the vertical distance between adjacent layers may be much shorter than the width of a single-layer chip, IC circuits with a three-dimensional structure can shorten the linking distances of devices disposed on a chip. Accordingly, their operational speed can be increased when a chip is designed with a vertical packed structure in 3D IC schemes. In order to integrate different devices in one single stacked structure chip, interconnects are required between die and die to electrically connect the devices on each level. The through silicon via (TSV) is one of the novel semiconductor techniques developed for this purpose. TSV technique produces devices that meet the market trends of “light, thin, short and small” through the 3D stacking technique and also provides wafer-level packages utilized in micro electronic mechanic system (MEMS), photo-electronics and electronic devices.
Nowadays, the TSV structure is usually obtained by performing the following steps: first, forming via hole on the front side of a wafer by etching or laser process. Secondly, filling the via hole with a conductive material, such as polysilicon, copper or tungsten, to form a conductive path (i.e. the interconnect structure). Finally, the back side of the wafer, or die, is thinned to expose the conductive path. After the manufacture of the TSV, the wafers or dies are stacked together so that their conductive paths are connected to each other to provide electrical connection between wafers or dies. The 3D-stacked IC structure is accordingly obtained.